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4-4. Timing Pulse Generation Circuit
4-4-1. Sync Separation Circuit (IC308)
The sync signal is separated from the INT V signal to generate the COMP SYNC signal (CLP signal), VD signal (V SYNC signal), and HD signal (AFC pulse). The frequency of the HD signal is stabilized in the AFC circuit.
4-4-6. APC Circuit (IC332 to 338)
In the NTSC mode, the voltage of the chroma burst period of the demodulated R-Y signal (APC PR signal) is sampled by IC336 (2/3) and held by IC334. This voltage is compared with the reference voltage at IC335 (1/2) and VCO (IC338, X301, 302, D302) is controlled by the error voltage so that the voltage of the chroma burst period of the R-Y signal coincides with the reference voltage. The reference voltage is set by the PHASE voltage. In the PAL mode, the polarity of the R-Y signal is inverted every 1H, and consequently, the polarity of the APC error line sampling hold circuit (IC336 (2/3), 334) and inversion line sampling hold circuit (IC336 (3/3), 333 (2/2)) are provided separately.
4-4-2. B.G.P Generation (IC310, 321)
The HD signal is delayed by the monostable multivibrator to generate the B.G.P. (burst gate pulse). The delay amount is set by the BGP-P voltage and the pulse width is set by the BGP-W voltage.
4-4-3. C.CL.P Generation/D1 HSYNC Delay Circuit (IC322, 352, 376)
In the D1 mode, the D1 HSYNC from the D1 decoder (IC115, 117) is delayed by the monostable multivibrator (IC376) to generate the delayed H sync. The delayed amount is set by the CCP-P voltage. In the other modes, the HD signal from the sync separation circuit (IC308) is delayed by the monostable multivibrator to generate the CCP.
4-5. Control Circuit
The CPU (IC802) performs serial communication with the main system controller by the three signals-MISO, MOSI, SCLK. It outputs the control signal for switching, etc. according to the instructions from the system controller. Some control signals are output from the extension port (IC807 to 809). The CPU also reads the adjustment data of the EEPROM (IC803) and outputs the adjustment data from the D/A converter (IC805, 806, 820). The CPU also transmits the color and black/white discrimination data (KILLER) of the input signals to the system controller.
4-4-4. HBLK Pulse Generation (IC311, 322)
The HD signal is delayed by the monostable multivibrator to generate the HBLK (horizontal blanking) pulse. The pulse width is set by the HBLK-W voltage.
4-4-5. KILLER Detection (IC325, 327, 326)
The voltage of the chroma burst period of the demodulated B-Y signal (APC PB signal) is sampled by IC327 (3/3) and held. This voltage is compared with the reference voltage (KILLER-LEVEL voltage) in IC326 (2/2) to discriminate between color and black/white.
4-4 (E)
BKM-21D
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