This document is just what I was looking for, it´s very useful, it contains adjustment procedures for the final stage of the power amp and also
has a complete wiring diagram and description of the main semiconductors used in the design.
Text excerpt from page 55 (click to view)
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6.4 FREQUENCY CHECK FOR CLOCK
A
- PCL output
In the normal operation mode (with the detachable panel installed, the ACC switched ON, the standby mode cancelled), shift the TESTIN (Pin 86) terminal to H. The clock signal is output from the PCL terminal (Pin 37). The frequency of the clock signal is 312.500kHz that is one 32nd of the fundamental frequency. The clock signal should be 312.500kHz ± 13Hz. If the clock signal is out of the range, the X'tal (X601) should be replaced with new one.
