SONY HDVF-7700
Service Manual

1-9. Theory Of Operation

6. Video Circuit (VF-69 board) The video color difference signals (Pr, Pb, Y) from the input connector is supplied to CN1 of the VF-69 board and terminated at 75 ohm. Each signal is input to the noise canceller circuit composed of Q401/ Q404, Q405/Q408, and Q409/Q412 to eliminate the noise components. Q413 and Q414 supplies bias voltage to the noise canceller circuit. DC component is reproduced by Q415, Q416 and Q417, the sync signal component is cut by the analog switch (IC402) and supplied to the amplifier in the next stage via the buffers composed of Q419/Q420, Q421/Q422, and Q423/Q424. IC401 supplied voltage for setting the DC reproducing level and this level can be adjusted by RV401. Q418 amplifies the sync signal and supplies it to IC402. By turning OFF the switch during the synch period, the sync signal is eliminated. IC403 and IC404 set the pulse phase and pulse width of the vertical sync pulse to be eliminated. Only the Y signal is also supplied to the sync separator IC5 from the latter stage of the noise canceller circuit. The VD signal obtained by sync separator is output from pin 4 and supplied to the vertical circuit via the buffer (Q26). The H SYNC signal output from pin 2 is supplied to IC6, and the equalizing pulse is eliminated. And the signal is then supplied to each circuit via the buffer (Q27) while the other is supplied to pin 11 of IC7, phase-adjusted, and used as the clamp pulse for DC reproduction in the previous phase-adjusted stage. The HD pulse output from pin 1 of CN801 is input to pin 4 of IC9, pulse width adjusted. One is then input to pin 4 of IC7 via buffer Q28 while the other is input as the HP (H pulse) to pin 20 of IC8. IC7 re-adjusts the pulse width, and inputs it as the clamp pulse to the base of Q418, and pins 23 and 24 of IC8. The VP (V Pulse) from pin 14 of CN801 is input to pin 18 of IC8 as VP via the buffer Q29 and also to each circuit as the blanking pulse of the vertical flyback period. The sync part of the Pr signal, Pb signal, and Y signal is eliminated and the Pr signal is delayed and amplified according to the peaking frequency by Q1 to Q7 and the Pb signal by Q8 to Q14. IC1 switches the delay time while IC2 switches between the monochrome processing and color processing. The MONO/COLOR signal of the camera is supplied to Q33 from pin 31 of CN801, and IC2 is controlled by Q33. The Y signal is supplied to the buffer Q15. When the peaking frequency is 16 MHz, it is sent to the peaking amplifier composed of Q16 to Q19. When the peaking frequency is 8 MHz, it is sent to the peaking amplifier composed of Q22 to Q25. The gain is adjusted by the amplifier Q20 and supplied to IC8 via the buffer Q21. When the switch connected to pins 1 and 2 of CN2 is ON, voltage is supplied to the gate of Q17 or Q23 by the peaking control volume connected to pins 3 to 5 of CN2 in the same way to adjust the gain of the peaking amplifiers. IC3 operates as the peaking frequency switch. S1 and Q32 control the switch and the peaking switching signal from the camera is input to the Q32 base from pin 30 of CN801. Q30 and Q31 are circuits which can supply the gain control voltage to the peaking circuit directly via D1. Q31 operates as a switch. The peaking up signal of the camera is supplied to the Q31 base from pin 2 of CN801. When ON, the peaking gain is set to maximum forcibly. Signals passing through the delay circuit and peaking amplifier are input to pin 3 from pin 1 of IC8 and processed inside IC8. The signal input to the Y color difference input (pin 1, pin 2, and pin 3) is pedestal clamped taking the signal input to the CLP1 (pin 24) as the clamp pulse. It is then supplied to the HUE and COLOR control blocks. The Y color difference signal controlled for HUE and COLOR is input to the MATRIX circuit, converted to the R/G/B prime color signals, and input to the video switch block. The R/G/B signal selected by the switch block is then output via the picture, gamma, bright, drive, and auto cut off control.
HDVF-7700

1-23 (E)