SONY PCS-I520
Service Manual

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(PCS-5100/5100P·E) 103
The sampling frequency for the Y-signal is 770 times of the input horizontal sync frequency, and that for the U, V signals is 385 times i.e., half of that for the Y-signal, of the input horizontal sync frequency. (For example, when VGA 60 Hz is input: 24.2 MHz, when SVGA 75 Hz is input: 36.1 MHz) The clock signal frequency is maintained to be an integer multiple of the input sync signal frequency to be used for AD conversion, is written into the memory of the scanning line conversion block, and is read from the memory using the NTSC or PAL clock (13.5 MHz) signal. Thus the horizontal picture size (number of dots in horizontal direction) is kept to be an appropriate value after the video signal is converted to the NTSC or PAL signal regardless of the input format if it is VGA or SVGA format.

3-21-6. Scanning Line Conversion Block (Input Side) (schematic diagram 5/8)
The number of pixels in the horizontal direction is adjusted by PLL fixed the dividing ratio of the sampling frequency during AD conversion to convert the VGA and SVGA to NTSC or PAL signals. However, this scanning line conversion block performs the scanning line conversion by using the weighted addition between the two lines in the vertical direction. The AD-converted U, V signals are time-base multiplexed by IC104, IC105, IC106 and IC109 so that they are formed into the 8-bit signal which is sent to the field memory (IC115, IC116). Because the Y-signal and the U, V signals use the different sampling frequencies, the different low-pass filters are used before AD conversion. And amount delay due to AD conversion is different in these signals so that the delay time difference between the Y-signal and the U, V signals occurs and is minimized by passing the AD converted digital Y-signal only through a shift register (IC102). (Number of shift registers to be used is switched by the horizontal sync frequency high/low detection signal. (IC103)) Then the Y-signal is sent to the field memory (IC113, IC114). The clock signal, horizontal sync signal and the vertical sync signal that are generated by the sync system (input side) are passed thorough 74VHC244 (IC107) and 74VHC157 (IC108), and are input to the memory controller (ispLSI1032E: IC119) via IC109, IC110 and IC111. On the other hand, the horizontal sync signal that is regenerated by PLL, and the vertical sync signal which is synchronized with the horizontal sync signal are input to the memory controller (ispLSI1032E: IC119). The field memory (IC113, IC114, IC115, IC116) is controlled by the timing pulse that is generated by the memory controller (IC119). The Y, U and V signals are written to the field memory (IC113, IC114, IC115, IC116) in synchronism with the sampling clock. This writing is performed into IC113/IC114 (Y) and IC115/IC116 (U, V) alternately every other horizontal line. Reading from the field memory is controlled by the memory controller IC119, and is performed in synchronism with the clock (13.5 MHz) of NTSC and PAL (ITU-R601). This clock signal is the same as that of the sync system of the output side. The free-running clock (27 MHz) that is generated by the DAD-017/017P board is input through the VPR-019 board, and is frequency-divided by two. When the video data is read from the field memory, reading is performed in a way that some horizontal lines are read out sequentially, some horizontal lines are read out repeatedly while a horizontal line is skipped. The two outputs from the respectively field memories are sent to the weighted adder where the data is added while the coefficient to be multiplied is changed in every horizontal line. This coefficient is also controlled by the memory controller IC119. The added output is sent to the VPR-019 board via CN2.

3-21-7. Menu Signal Input Block (schematic diagram 6/8)
The menu signal that is multiplexed with the output video signal of the DAD-33/33P board, is generated by the DAD-017/017P board and is sent to this board with 4-bit data of Y, U and V signals respectively in synchronism with the 13.5 MHz clock of the output system. Among the Y, U and V signals, the U and V signals are deduced respectively to 1/2 by IC122 in order to match the signal format with other video signals, and then is time-multiplexed into single 4-bit signal by IC123. The U and V signals and the Y-signal that has passed through IC121 are the 4-bit signals and are super-imposed with other signals at the selector (IC126, IC127) as the higher 4-bit signal of the 8-bit data. The YS signal that generates the timing for multiplexing the menu signal, is sent to ispLSI1016E (IC10) that is the input signal format detector and is at the same time the output selector controller. IC10 controls the output signal selector (IC126, IC127) using the information such as the control bit and blanking signal that are supplied from the I/O port of the DAD-017/017P board.

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(PCS-P500/P500P SERVICE MANUAL Volume 1)