SONY WRT-800A
Service Manual

Description
WRT-800A is comprised of the following: AU-258 board Audio circuit block ............................. Ref. No. 100s Power supply circuit block ................. Ref. No. 200s RF-87 board CPU and peripheral circuit block ....... Ref. No. 300s RF circuit block .................................. Ref. No. 400s AU-258 board . Audio circuit block The audio signal which is input from the input connector (CN101) is input to the pre amplifier circuit (IC101 (1/2)). The audio signal which is amplified by IC101 is input to the compressor circuit (IC102). The audio signal is compressed to a signal level of 2:1 (1/2) by the compressor circuit and then inputs to the limiter circuit (IC103, IC104, Q101). Limiter level is adjusted by the RV101. The limiter control signal is fed back from Q101 to the compander circuit (IC102) and activates the limiter operations. The audio signal is output to the limiter circuit and the preemphasis circuit (IC101(2/2)). Note that time constant for the pre-emphasis is 50us. The audio signal which is output from the pre-emphasis circuit is input to the clipper circuit (Q102,Q103). The clipping level is adjusted by the RV102. The audio signal that has been clipped when the input signal amplitude is high, is wave-shaped by the low-pass filter (Q104). The audio signal is mixed with the tone signal (X102; 32.768 kHz) and battery alarm signal (X101; 32.782 kHz), and inputs to the analog switch (IC107). The tone signal level and battery alarm signal level are adjusted by the RV103. The mixed audio signal is sent to RF circuit block (VCO, CP401) of RF-87 board via the reference level control (RV104). . Power supply circuit block The DC-DC converter circuit (IC201, Q202, Q203) extracts the 3 V (VCC) from the battery voltage (0.9 to 1.8 V) and supplies to individual circuits. Each of operation timing is controlled by the CPU (IC301). The DC-DC converter IC (IC201) is turned ON and OFF by the power switch circuit (D202, Q201) which is originally controlled to be switched ON and OFF by the POWER switch (S201). The diode D201 of the power switch circuit supplied power to the DC-DC converter IC (IC201) during when the main power is ON to assist building up IC201 when the main power is turned on. When the POWER switch (S201) is turned OFF, Q201 detects the OFF state of the POWER switch (S201) and sends the detection signal to CPU (IC301). This is done to
WRT-800A (CE)

turn off the tone signal before the RF carrier signal is turned off. The power supply voltage 3 V (VCC) for circuit is turned off about one second after the POWER switch (S201) is switched to OFF position. . Battery indicator IC306 always monitors the battery voltage. When the battery voltage drops to 1.0 V, IC306 sends the detection signal to CPU (IC301). The battery alarm signal is oscillated at all times by an oscillator circuit (IC105 (1/6), X101: 32.782 kHz). When the switching circuit (IC106) is turned on by the control signal (LVD signal) from CPU (IC301), the battery alarm signal is super-imposed on the RF carrier signal. At the same time, the battery indictor LED (D301) of the main unit is turned off. The other device which monitors the battery voltage is IC307. IC307 sends the detection signal to CPU (IC301) when the battery voltage drops to 0.9 V. This is done to turn off the tone signal and the RF carrier signal before the circuit becomes unstable.

RF-87 board . CPU and the peripheral circuit block The CPU (IC301) is a 4-bit microprocessor, and the clock is used a 4 MHz (X301, IC303). This clock signal is sent to IC104 as the reference frequency signal of the PLL circuit. The transmission frequency is adjusted by CT301. The CPU sends out the PLL data, and controls the AF mute, RF mute, and so on. The voltage detector circuit (IC304, IC305) detects the power supply voltage (+2.7 V) and uses it to reset the CPU with dropping power supply voltage. . RF circuit block The oscillation circuit utilizes the PLL frequency synthesizer method. The VCO (CP401) is controlled by PLL IC (IC401). The carrier frequency is controlled by the serial data (PLL data) sent from the CPU to the PLL IC (IC401). The lock detection (Q401) detects the lock condition of the PLL by the output signal (LD signal) from the phase comparator in the PLL IC, and sends the signal to CPU (IC301). The RF signal which is oscillated and modulated by the VCO (CP401) is input RF amplifier circuit (Q404, Q405). The RF signal amplified by RF amplifier circuit is output from the antenna via the low-pass filter (FL401) and isolator (CP402). The voltage control circuit (Q402, Q403, D403) performs ON/OFF control of the power voltage for the RF circuit. This control signal is the RFM signal from the CPU (IC301). RF output level is adjusted by the RV401. 4-2